Currently, a polysilicon (“poly”) cap layer with high tensile stress is utilized to improve the performance of NMOS semiconductor devices. The poly cap layer is deposited over the NMOS device after a source and drain ion implantation and prior to a source and drain anneal. As the source and drain are annealed, the re-crystallization retains the stress of the poly cap layer formed over the source and drain. The tensile strain introduced into the source and drain improves charge carrier mobility in the NMOS device.
Typically, the poly cap layer is also formed over other semiconductor devices contained in the wafer, such as PMOS devices. The source and drain of both the PMOS and NMOS devices are subjected to an anneal, simultaneously, in order to re-crystallize the silicon of both the PMOS and NMOS devices. However, the high tensile stress of the poly cap layer does not improve the performance of the PMOS device. In fact, the PMOS device's performance may be degraded by the presence of the poly cap layer during the source and drain anneal. As such, processes are needed that allow tensile stain to be introduced into an NMOS device without adversely affecting a PMOS device.